Senior Manager-FPGA IP and System Design - Prodigy Technovations

Job description Senior Manager-FPGA IP and System Design - Prodigy Technovations Protocol Exercisers & Analyzers Logic Analyser Oscilloscope oftware Protocol Analyzer Logic Analyzer Prodigy Partner Central Other Protocols Search for: Search Button What can we help you find? Responsibilities As a Sr. Engineering will be working on our existing and next generation Protocol Analyzers and exercisers and similar products. Manages the FPGA and Board design team. Develop a new products to meet needs top semiconductor for their pre and post silicon validation. The role involves contributing to the entire FPGA based product development flow starting from requirement analysis till final product testing in lab environment. The candidate will be responsible for architecture/micro-architecture design and implementation of the logic in Verilog for targeted FPGA, writing test benches to validate the design etc. Job involves working with team of FPGA Design Engineers and deliver the products as planned. Guides the team to Debugging of designs to resolve complex design issues. Job involves frequent interaction with board design, software, testing and lab teams to deliver the product meeting the customer requirements. Job involves understanding and working with interfaces such as PCIe, GigE, MPHY/UFS, DPHY/CSI/DSI, USB, SD, eMMC, I3C/I2C, SPI/QSPI etc. Contributing to/participating in internal design reviews to ensure adherence to the company FPGA design process. Maintaining all design documents and code base in SVN. Participate and contribute to the standard bodies such as PCIeSig, MIPI Alliance, SD Association, and USB Org. Owns responsibility filing patents. International travel is involved. Qualifications BE/ME in Electronics from a reputed college. Specialization in VLSI and Embedded Design is a plus. 12 to 15 years of experience in designing and implementing FPGA-based solution in Xilinx or Altera FPGA, preferably FPGA-based product development experience. Knowledgeable in board design. Must have experience in System Design with Xilinx/Altera FPGA devices with relevant tools. Deep expertise in FPGA-based data plane design to manage the high-speed serial bus data. Must have experience in Verilog and/or VHDL coding. Must have very good understanding of physical layer of SERDES of XILINX-AMD or Intel FPGA. Job Features Job Category Apply Online A valid email address is required. A valid phone number is required. Our team represents a talented, experienced, and highly specialized group of development engineers, sales and marketing specialists. Through many years of direct engineering involvement with our customers, our personnel have developed expertise in wide range of technologies in serial data. Quick links Contact info Prodigy Technovations Pvt Ltd #294, 3rd Floor, 7th Cross, 7th Main, BTM II Stage,Bangalore 560 076 | India +91 80 4212 6100 contact@prodigytechno.com UFS 4.0 PGY-UFS4.0-PA, UFS Protocol Analyzer is the industry-first working and tested UFS4.0 Protocol Analyzer. It offers protocol data capture and debugging of data across MPHY, UniPro, and UFS protocol layers Role: UX, Design & Architecture - Other Industry Type: Hardware & Networking Department: UX, Design & Architecture Employment Type: Full Time, Permanent Role Category: Other Design Education UG: Any Graduate PG: Any Postgraduate Key Skills VHDLSemiconductorVLSIFPGACodingUSBVerilogSystem designSPIAutomotive